The invention relates to a microprogram control system.
Information processing systems have recently been adopting an arrangement in which a plurality of arithmetic circuits each performing a different type of arithmetic operation are arranged near the corresponding microprogram control units holding microprograms for controlling the arithmetic circuits. This is because the time which a signal takes to travel from a microprogram control unit to the corresponding arithmetic circuit can be reduced by placing the microprogram control unit adjacent to the arithmetic circuit. In this arrangement, a case takes place in which a microprogram control unit (I) in operation needs to have an arithmetic operation performed which its associated arithmetic circuit cannot perform, and therefore the unit (I) requests another microprogram control unit (II) at rest to take over its processing. In this case, in the unit (II) the status information, stored in the conditional register of the unit (I), from the arithmetic circuit controlled by the unit (I) becomes necessary when a conditional branch microinstruction which determines a branch address on the basis of the status information is read out of the unit (II). In prior art systems, such status information from the arithmetic circuits is stored, under the control of extra microinstructions, in an extra common memory which can be accessed by a plurality of microprogram control units.
Further, when a single-bit error is detected, for example, by a parity check technique, in a microinstruction stored in the unit (I) for starting the unit (II), such microinstruction including a start command and a start address, the start command or the start address may be incorrect. In this case, the unit (I) sends a cancel signal to a dedicated cancel circuit located adjacent to the arithmetic circuit associated with the unit (II), to cancel the start command and the start address sent to the unit (II). In response to the cancel signal, the cancel circuit sets the bit pattern of the microinstruction to be supplied to the arithmetic circuit from the unit (II) forcibly to all zeros. In this prior art system, such a cancel circuit must be provided near each arithmetic circuit.